module top (
    input               clk,
    input               rst,
    input  wire [ 7:0]  bcd_in,
    output reg  [11:0]  bcd_out_reg 
);
wire [11:0] bcd_out;
    BtoD inst_BtoD (.bcd_in(bcd_in), .bcd_out(bcd_out));
always@(posedge clk)
    if(rst)
        bcd_out_reg <= 12'b0;
    else 
        bcd_out_reg <= bcd_out;

endmodule
